Medias
Skew-Tolerant Circuit Design
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While seni
...
Spécifications techniques
Date de sortie | 20 avril 2015 |
Langue | Anglais |
Éditeur | Morgan Kaufmann |
Accessibilité | Aucune information disponible concernant l'accessibilité pour le format ePub |